The present invention relates to phase-locked loops (PLLs), and more particularly, to an adaptive frequency detector in a PLL.
A phase locked loop (PLL) has many usages, such as clock/data recovery, frequency or phase modulation/demodulation, and generating a clock having stable frequency, so that phase locked loops are widely applied in various electronic devices, consumer products, and communication devices.
In general, a conventional PLL has a phase detector (PD) and a frequency detector (FD). The phase and frequency detector are used for detecting phase error and frequency error, respectively, between an input signal and a feedback signal. The conventional PLL uses a loop filter to adjust the operation of a voltage-controlled oscillator (VCO) according to the detection result of the phase detector and frequency detector until the frequency and phase of the feedback signal match that of the input signal.
Please refer to FIG. 1, which depicts a simplified block diagram of a conventional PLL 100. The PLL 100 has a phase detector 110 for comparing the phase difference between the input signal and the feedback signal. The phase detector 110 adjusts the output current of a phase-error current source 130 by controlling the phase-error current source 130 to charge or discharge according to the phase difference between the input signal and the feedback signal. The PLL 100 further has a frequency detector 120 for comparing the frequency difference between the input signal and the feedback signal. The frequency detector 120 adjusts the output current of a frequency-error current source 140 by controlling the frequency-error current source 140 to charge or discharge according to the frequency difference between the input signal and the feedback signal. In practical implementations, the phase-error current source 130 and the frequency-error current source 140 can be implemented with charge pumps.
The PLL 100 further comprises a loop filter 150 for generating a control voltage according to the sum of currents generated from the phase-error current source 130 and the frequency-error current source 140. The PLL 100 further includes a voltage-controlled oscillator (VCO) 160 for adjusting the frequency of the feedback signal according to the control voltage generated from the loop filter 150 to ensure the frequency and phase of the feedback signal match that of the input signal.
As is well known in the art, the pulse width of the phase error signal generated from the phase detector 110 represents the phase error between the input signal and the feedback signal. However, the pulse width of the frequency error signal generated from the frequency detector 120 is fixed. Therefore, the frequency-error current source 140 influences the performance of the conventional PLL 100. If the PLL 100 uses a frequency-error current source with large output current, the frequency detector 120 may have difficultly converging to the lock-in range. On the other hand, if the PLL 100 uses a frequency-error current source with small output current, the lock-in operation of the PLL 100 may be excessively slow. Moreover, if the maximum output current of the frequency-error current source 140 is too small, the PLL 100 may be unable to enter the locked state.